Verilog Basics

This page introduces Verilog HDL through a very simple and practical example. You will write your first Verilog module, simulate it, and verify its behavior.

Do not rush. Understanding this page properly will make everything else easier.

What is Verilog?

Verilog is a Hardware Description Language (HDL) used to describe digital circuits. Unlike C or Python, Verilog describes hardware behavior and structure.

Engineers use Verilog to design logic such as gates, multiplexers, registers, ALUs, and complete processors.

Step 1: Write Your First Verilog Design (AND Gate)

Create a file named and_gate.v and write the following code:

module and_gate(
  input a,
  input b,
  output y
);
  assign y = a & b;
endmodule

This is a purely combinational design. The output y is HIGH only when both inputs are HIGH.

Step 2: Write a Testbench

The testbench applies different inputs to your design and generates a waveform.

module and_gate_tb;
  reg a, b;
  wire y;

  and_gate uut(.a(a), .b(b), .y(y));

  initial begin
    $dumpfile("and_gate.vcd");
    $dumpvars(0, and_gate_tb);

    a = 0; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 0;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Step 3: Run Simulation

Open WSL terminal and go to your project folder:

iverilog -o and_gate_tb.vvp and_gate.v and_gate_tb.v
vvp and_gate_tb.vvp
gtkwave and_gate.vcd

GTKWave will open. Add signals a, b, and y to the waveform window.

Success ✅

If the waveform shows y = a & b, you have successfully written and simulated your first Verilog design.

This is the same fundamental process used in real VLSI projects.

What’s Next?

Next, we will explore more Verilog concepts and begin moving toward synthesis and real ASIC-style flow.

Continue Learning